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MAXQ61H 16-bit microcontroller with infrared module ________________________________________________________________ maxim integrated products 1 19-4604; rev 0; 5/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the MAXQ61H is a low-power, 16-bit maxq micro- controller designed for low-power applications includ- ing universal remote controls, consumer electronics, and white goods. the MAXQ61H combines a powerful 16-bit risc microcontroller and integrated peripherals including an ir module with carrier frequency genera- tion and flexible port i/o capable of multiplexed keypad control. the MAXQ61H includes 36kb of rom memory and 1.28kb of data sram. for the ultimate in low-power battery-operated perfor- mance, the MAXQ61H includes an ultra-low-power stop mode (0.2?, typ). in this mode, the minimum amount of circuitry is powered. wake-up sources include exter- nal interrupts, the power-fail interrupt, and a timer inter- rupt. the microcontroller runs from a wide 1.70v to 3.6v operating voltage. applications remote controls battery-powered portable equipment consumer electronics home appliances white goods features ? high-performance, low-power 16-bit risc core ? dc to 12mhz operation across entire operating range ? 1.70v to 3.6v operating voltage range ? 33 total instructions for simplified programming ? three independent data pointers accelerate data movement with automatic increment/decrement ? dedicated pointer for direct read from code space ? 16-bit instruction word, 16-bit data bus ? 16 x 16-bit general-purpose working registers ? memory features 36kb rom 1.28kb data sram ? additional peripherals power-fail warning power-on reset/brownout reset automatic ir carrier frequency generation and modulation two 16-bit, programmable timers/counters with prescaler and capture/compare programmable watchdog timer 8khz nanopower ring oscillator wake-up timer up to 24 (MAXQ61Ha) general-purpose i/os ? low power consumption 0.2? (typ), 2.0? (max) in stop mode t a = +25?, power-fail monitor disabled 2.0ma (typ) at 12mhz in active mode note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of a ny device may be simultaneously available through various sales channels. for information about device errata, go to: www.maxim-ic.com/errata . note: contact factory for information about masked rom devices. + denotes a lead(pb)-free/rohs-compliant package. * contact factory for availability. ** ep = exposed pad. pin configuration appears at end of data sheet. maxq is a registered trademark of maxim integrated products, inc. part temp range operating voltage (v) program memory (kb) data memory (kb) pin-package MAXQ61Ha-0000+ 0c to +70c 1.70 to 3.6 36 rom 2 32 tqfn-ep** MAXQ61Hx-0000+* 0c to +70c 1.70 to 3.6 36 rom 2 bare die ordering information/selector guide
MAXQ61H 16-bit microcontroller with infrared module 2 _______________________________________________________________________________________ absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 stack memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 utility rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 ir carrier generation and modulation timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 carrier generation module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 ir transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 ir transmit?ndependent external carrier and modulator outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 ir receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 carrier burst-count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 16-bit timers/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 general-purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 power-fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 grounds and bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 additional documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 development and technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table of contents
MAXQ61H 16-bit microcontroller with infrared module _______________________________________________________________________________________ 3 table 1. watchdog interrupt timeout (sysclk = 12mhz, cd[1:0] = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 2. power-fail detection states during normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 3. stop mode power-fail detection states with power-fail monitor enabled . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 4. stop mode power-fail detection states with power-fail monitor disabled . . . . . . . . . . . . . . . . . . . . . . . . . .20 list of tables figure 1. ir transmit frequency shifting example (ircfme = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 2. ir transmit carrier generation and carrier modulator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 3. ir transmission waveform (ircfme = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 4. external irtxm (modulator) output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 5. ir capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 6. receive burst-count example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 7. on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 8. power-fail detection during normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 9. stop mode power-fail detection states with power-fail monitor enabled . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 10. stop mode power-fail detection with power-fail monitor disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 list of figures
MAXQ61H 16-bit microcontroller with infrared module 4 _______________________________________________________________________________________ recommended dc operating conditions (v dd = v rst to 3.6v, t a = 0? to +70?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v dd with respect to gnd .......-0.3v to +3.6v voltage range on any lead with respect to gnd except v dd ..................................... -0.3v to (v dd + 0.5v) operating temperature range...............................0? to +70? storage temperature range .............................-65? to +150? soldering temperature...........................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units supply voltage v dd v rst 3.6 v 1.8v internal regulator v reg18 1.62 1.8 1.98 v power-fail warning voltage for supply (note 2) v pfw monitors v dd 1.75 1.8 1.85 v power-fail reset voltage (note 3) v rst monitors v dd 1.64 1.67 1.70 v power-on reset voltage v por monitors v dd 1.0 1.45 v ram data-retention voltage v drv (note 4) 1.0 v active current (note 5) i dd_1 sysclk = 12mhz 2.5 3.75 ma t a = +25 c 0.15 2.0 i s1 power-fail off t a = 0c to +70 c 0.15 8 t a = +25 c 22 31 stop-mode current i s2 power-fail on t a = 0c to +70 c 27.6 38 a current consumption during power-fail i pfr (notes 4, 6) [(3 x i s2 ) + ((pci - 3) x (i s1 + i nano ))]/pci a power consumption during power-on reset i por (note 7) 100 na stop-mode resume time t on 375 + 8192t hfxin s power-fail monitor startup time t prm_on (note 4) 150 s power-fail warning detection time t pfw (notes 4, 8) 10 s input low voltage for irtx, irrx, reset , and all port pins v il gnd 0.3 x v dd v input high voltage for irtx, irrx, reset , and all port pins v ih 0.7 x v dd v dd v input hysteresis (schmitt) v ihys 300 mv input low voltage for hfxin v il_hfxin gnd 0.3 x v dd v absolute maximum ratings
MAXQ61H 16-bit microcontroller with infrared module _______________________________________________________________________________________ 5 recommended dc operating conditions (continued) (v dd = v rst to 3.6v, t a = 0? to +70?.) (note 1) parameter symbol conditions min typ max units input high voltage for hfxin v ih_hfxin 0.7 x v dd v dd v irrx input filter pulse-width reject t irrx_r 50 ns irrx input filter pulse-width accept t irrx_a 200 ns v dd = 3.6v, i ol = 25ma (note 4) 1.0 v dd = 2.35v, i ol = 10ma (note 4) 1.0 otuput low voltage for irtx v ol_irtx v dd = 1.85v, i ol = 4.5ma 1.0 v v dd = 3.6v, i ol = 11ma (note 4) 0.4 0.5 v dd = 2.35v, i ol = 8ma (note 4) 0.4 0.5 output low voltage for reset and all port pins (note 9) v ol v dd = 1.85v, i ol = 4.5ma 0.4 0.5 v output high voltage for irtx and all port pins v oh i oh = -2ma v dd - 0.5 v dd v input/output pin capacitance for all port pins c io (note 4) 15 pf input leakage current i l internal pullup disabled -100 +100 na v dd = 3.0v, v ol = 0.4v (note 4) 16 28 39 input pullup resistor for reset , irtx, irrx, and all port pins r pu v dd = 2.0v, v ol = 0.4v 17 30 41 k external crystal/resonator crystal/resonator f hfxin dc 12 mhz crystal/resonator period t hfxin 1/f hfxin ns crystal/resonator warmup time t xtal_rdy from initial oscillation 8192 x t hfxin ms oscillator feedback resistor r oscf (note 4) 0.5 1.0 1.5 m external clock input external clock frequency f xclk dc 12 mhz external clock period t xclk 1/f xclk ns external clock duty cycle t xclk_duty 45 55 % f hfin system clock frequency f ck hfxout = gnd f xclk mhz system clock period t ck 1/f ck mhz nanopower ring oscillator t a = +25 c 3.0 8.0 20.0 nanopower ring oscillator frequency f nano t a = +25 c, v dd = por voltage (note 4) 1.7 2.4 khz nanopower ring oscillator duty cycle t nano (note 4) 40 60 % nanopower ring oscillator current i nano typical at v dd = 1.64v, t a = +25 c (note 4) 40 400 na
MAXQ61H 16-bit microcontroller with infrared module 6 _______________________________________________________________________________________ recommended dc operating conditions (continued) (v dd = v rst to 3.6v, t a = 0? to +70?.) (note 1) parameter symbol conditions min typ max units wake-up timer wake-up timer interval t wakeup 1/f nano 65,535/ f nano s ir carrier frequency f ir (note 4) f ck /2 hz note 1: specifications to 0? are guaranteed by design and are not production tested. note 2: the power-fail warning monitor and the power-fail reset monitor track each other with a minimum delta between the two of 0.11v. note 3: the power-fail reset and power-on-reset (por) detectors operate in tandem to ensure that one or both signals are active at all times when v dd < v rst . doing so ensures the device maintains the reset state until the minimum operating voltage is achieved. note 4: guaranteed by design and not production tested. note 5: measured on the v dd pin and the part not in reset. all inputs are connected to gnd or v dd . outputs do not source/sink any current. note 6: the power-check interval (pci) can be set to always on, 1024, 2048, or 4096 nanopower ring oscillator clock cycles. note 7: current consumption during por when powering up while v dd < v por . note 8: the minimum amount of time that v dd must be below v pfw before a power-fail event is detected. note 9: the maximum total current, i oh (max) and i ol (max), for all listed outputs combined should not exceed 32ma to satisfy the maximum specified voltage drop. this does not include the irtx output.
MAXQ61H 16-bit microcontroller with infrared module _______________________________________________________________________________________ 7 pin description pin name function power pins 14, 30 v dd supply voltage 13 regout regulator capacitor. this pin must be connected to ground through a 1. 0f external ceramic- chip capacitor in series with a 2 to 10 resistor. the capacitor must be placed as close to this pin as possible . no other external devices other than the capacitor should be connected to this pin. ep (gnd) exposed pad/ground. the gnd contact is through the exposed paddle located on the underside of the package. it must be directly connected to the gr ound pl ane. reset pins 29 reset digital, active-low, reset input/output. the cpu is held in reset when this pin is low and begins executing from the reset vector when released. the pin includes pullup current source and should be driven by an open-drain, external source capable of sinking in excess of 4ma. this pin is driven low as an output when an internal reset condition occurs. clock pins 17 hfxin 18 hfxout high-frequency crystal input. connect an external crystal or resonator between hfxin and hfxout as the high-frequency system clock. alternatively, hfxin is the input for an external, high-frequency clock source when hfxout is floating. ir function pins 31 irtx ir transmit output. ir transmit pin capable of sinking 25ma. this pin defaults to a high- impedance input with the weak pullup disabled during all forms of reset. software must configure this pin after release from reset to remove the high-impedance input condition. 32 irrx ir receive input. ir receive pin. this pin defaults to a high-impedance input with the weak pullup disabled during all forms of reset. software must configure this pin after release from reset to remove the high-impedance input condition. general-purpose i/o and special function pins general-purpose, digital, i/o, type-d port. these port pins function as bidirectional i/o pins. all port pins default to high-impedance mode after a reset. software must configure these pins after release from reset to remove the high-impedance input condition. all alternate functions must be enabled from software. port 0 can opti onally be defined with int8Cint15. pin port special function 1 p0.0 irtxm/int8 2 p0.1 int9 3 p0.2 int10 4 p0.3 int11 5 p0.4 int12 6 p0.5 tba0/tba1/int13 7 p0.6 tbb0/int14 1C8 p0.0Cp0.7; irtxm; tba0, tba1; tbb0, tbb1; int8Cint15 8 p0.7 tbb1/int15
MAXQ61H 16-bit microcontroller with infrared module 8 _______________________________________________________________________________________ pin description (continued) pin name function general-purpose, digital, i/o, type-d port; external edge-selectable interrupt. these port pins function as bidirectional i/o pins or as interrupts. all port pins default to high-impedance mode after a reset. software must configure these pins after release from reset to remove the high- impedance input condition. all interrupt functions must be enabled from software. pin port special function 9 p1.0 int0 10 p1.1 int1 11 p1.2 int2 12 p1.3 int3 15 p1.4 int4 16 p1.5 int5 19 p1.6 int6 9C12, 15, 16, 19, 20 p1.0Cp1.7; int0Cint7 20 p1.7 int7 general-purpose, digital, i/o, type-c port. these port pins function as bidirectional i/o pins. software must configure these pins after release from reset to remove the high-impedance input condition. all alternate functions must be enabled from software. enabling the pins special function disables the general-purpose i/o on the pin. the jtag pins (p2.4Cp2.7) default to their jtag function with weak pullups enabled after a reset. the jtag function can be disabled using the tap bit in the sc register. p2.7 functions as the jtag test-data output on reset and defaults to an input with a weak pullup. the output function of the test data is only enabled during the taps shift_ir or shift_dr states. pin port special function 25 p2.4 tck 26 p2.5 tdi 27 p2.6 tms 25C28 p2.4Cp2.7; tck, tdi, tms, tdo 28 p2.7 tdo no connection pins 21C24 n.c. no connection
MAXQ61H 16-bit microcontroller with infrared module _______________________________________________________________________________________ 9 detailed description the MAXQ61H microcontroller provides integrated, low-cost solutions that simplify the design of ir commu- nications equipment such as universal remote controls. standard features include the highly optimized, single- cycle, maxq 16-bit risc core, 36kb of user rom memory, 1.28kb data ram, a soft stack, 16 general- purpose registers, and three data pointers. the maxq core offers the industry? best mips/ma rating, allowing developers to achieve the same performance as com- peting microcontrollers at substantially lower clock rates. combining reduced active-mode current with the MAXQ61H stop-mode current (0.2?, typical) results in increased battery life. application-specific peripherals include flexible timers for generating ir carrier frequen- cies and modulation, a high-current ir drive pin capa- ble of sinking up to 25ma current, and output pins capable of sinking up to 5ma ideal for ir applications, general-purpose i/o pins ideal for keypad matrix input, and a power-fail-detection circuit to notify the applica- tion when the supply voltage is nearing the minimum operating voltage of the microcontroller. at the heart of the MAXQ61H is the maxq 16-bit risc core. the MAXQ61H operates from dc to 12mhz and almost all instructions execute in a single clock cycle (83.3ns at 12mhz), enabling nearly 12mips true code operation. when active device operation is not required, an ultra-low-power stop mode can be invoked from software, resulting in quiescent current consump- tion of less than 0.2? (typ) and 2.0? (max). the com- bination of high-performance instructions and ultra-low stop-mode current increases battery life over compet- ing microcontrollers. an integrated por circuit with brownout support resets the device to a known condi- tion following a power-up cycle or brownout condition. additionally, a power-fail warning flag is set and a power-fail interrupt can be generated when the system voltage falls below the power-fail warning voltage, v pfw . the power-fail warning feature allows the appli- cation to notify the user that the system supply is low and appropriate action should be taken. microprocessor the MAXQ61H is based on maxim? low-power, 16-bit maxq family of risc cores. the core supports the harvard memory architecture with separate 16-bit pro- gram and data address buses. a fixed 16-bit instruction word is standard, but data can be arranged in 8 or 16 bits. the maxq core in the MAXQ61H family is imple- mented as a pipelined processor with performance approaching 1mips/mhz. the 16-bit data path is imple- mented around register modules, and each register module contributes specific functions to the core. the accumulator module consists of sixteen 16-bit registers and is tightly coupled with the arithmetic logic unit (alu). a configurable soft stack supports program flow. execution of instructions is triggered by data transfer between functional register modules or between a func- tional register module and memory. because data movement involves only source and destination mod- ules, circuit-switching activities are limited to active modules only. for power-conscious applications, this approach localizes power dissipation and minimizes switching noise. the modular architecture also provides a maximum of flexibility and reusability that is important for a microprocessor used in embedded applications. the maxq instruction set is highly orthogonal. all arith- metical and logical operations can use any register in conjunction with the accumulator. data movement is supported from any register to any other register. memory is accessed through specific data-pointer reg- isters with automatic increment/decrement support. memory the MAXQ61H incorporates several memory types that include the following: 36kb user rom 1.28kb sram data memory 1.024kb utility rom soft stack block diagram 16-bit maxq risc cpu 8khz nano ring 1.28kb sram ir timer 36kb user rom secure mmu 16-bit timer 16-bit timer gpio voltage monitor ir driver regulator watchdog clock 1.024kb rom MAXQ61H
MAXQ61H stack memory a 16-bit-wide internal stack provides storage for program return addresses and can also be used as general-pur- pose data storage. the stack is used automatically by the processor when the call, ret, and reti instruc- tions are executed and when an interrupt is serviced. an application can also store values in the stack explicitly by using the push, pop, and popi instructions. on reset, the stack pointer, sp, initializes to the top of the stack (0fh). the call, push, and interrupt-vector- ing operations increment sp, then store a value at the location pointed to by sp. the ret, reti, pop, and popi operations retrieve the value at sp and then decrement sp. utility rom the utility rom is a 1.024kb block of internal rom mem- ory that defaults to a starting address of 8000h. the utility rom consists of subroutines that can be called from application software. these include the following: test routines (internal memory tests, memory loader, etc.) user-callable routines for fast table lookup following any reset, execution begins in the utility rom. the rom software determines whether the program execution should immediately jump to location 0000h, the start of system code, or to one of the special rou- tines mentioned. routines within the utility rom are user accessible and can be called as subroutines by the application software. more information on the utility rom functions is contained in the maxq family user? guide: maxq610 supplement . watchdog timer an internal watchdog timer greatly increases system reliability. the timer resets the device if software execu- tion is disturbed. the watchdog timer is a free-running counter designed to be periodically reset by the appli- cation software. if software is operating correctly, the counter is periodically reset and never reaches its max- imum count. however, if software operation is interrupt- ed, the timer does not reset, triggering a system reset and optionally a watchdog timer interrupt. this protects the system against electrical noise or esd upsets that could cause uncontrolled processor operation. the internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing system cost and simultaneously increasing reliability. the watchdog timer functions as the source of both the watchdog-timer timeout and the watchdog-timer reset. the timeout period can be programmed in a range of 2 15 to 2 24 system clock cycles. an interrupt is generat- ed when the timeout period expires if the interrupt is enabled. all watchdog-timer resets follow the pro- grammed interrupt timeouts by 512 system clock cycles. if the watchdog timer is not restarted for another full interval in this time period, a system reset occurs when the reset timeout expires. see table 1. ir carrier generation and modulation timer the dedicated ir timer/counter module simplifies low- speed ir communication. the ir timer implements two pins (irtx and irrx) for supporting ir transmit and receive, respectively. the irtx pin has no correspond- ing port pin designation, so the standard pd, po, and pi port control status bits are not present. however, the irtx pin output can be manipulated high or low using the pwcn.irtxout and pwcn.irtxoe bits when the ir timer is not enabled (i.e., iren = 0). the ir timer is composed of two separate timing enti- ties: a carrier generator and a carrier modulator. the 16-bit microcontroller with infrared module 10 ______________________________________________________________________________________ wd[1:0] watchdog clock watchdog interrupt timeout watchdog reset after watchdog interrupt (s) 00 sysclk/2 15 2.7ms 42.7 01 sysclk/2 18 21.9ms 42.7 10 sysclk/2 21 174.7ms 42.7 11 sysclk/2 24 1.4s 42.7 table 1. watchdog interrupt timeout (sysclk = 12mhz, cd[1:0] = 00)
carrier generation module uses the 16-bit ir carrier register (irca) to define the high and low time of the carrier through the ir carrier high byte (ircah) and ir carrier low byte (ircal). the carrier modulator uses the ir data bit (irdata) and ir modulator time register (irmt) to determine whether the carrier or the idle con- dition is present on irtx. the ir timer is enabled when the ir enable bit (iren) is set to 1. the ir value register (irv) defines the begin- ning value for the carrier modulator. during transmis- sion, the irv register is initially loaded with the irmt value and begins down counting towards 0000h, whereas in receive mode it counts upward from the ini- tial irv register value. during the receive operation, the irv register can be configured to reload with 0000h when capture occurs on detection of selected edges or can be allowed to continue free-running throughout the receive operation. an overflow occurs when the ir timer value rolls over from 0ffffh to 0000h. the ir overflow flag (irov) is set to 1 and an interrupt is generated if enabled (irie = 1). carrier generation module the ircah byte defines the carrier high time in terms of the number of ir input clocks, whereas the ircal byte defines the carrier low time. ir input clock (f irclk ) = f sys /2 irdiv[1:0] carrier frequency (f carrier ) = f irclk /(ircah + ircal + 2) carrier high time = ircah + 1 carrier low time = ircal + 1 carrier duty cycle = (ircah + 1)/(ircah + ircal + 2) during transmission, the irca register is latched for each irv downcount interval and is sampled along with the irtxpol and irdata bits at the beginning of each new irv downcount interval so that duty-cycle variation and frequency shifting is possible from one interval to the next, which is illustrated in figure 1. figure 2 illustrates the basic carrier generation and its path to the irtx output pin. the ir transmit polarity bit (irtxpol) defines the starting/idle state and the carrier polarity of the irtx pin when the ir timer is enabled. ir transmission during ir transmission (irmode = 1), the carrier gener- ator creates the appropriate carrier waveform, while the carrier modulator performs the modulation. the carrier modulation can be performed as a function of carrier cycles or irclk cycles dependent on the setting of the ircfme bit. when ircfme = 0, the irv downcounter is clocked by the carrier frequency and thus the modula- tion is a function of carrier cycles. when ircfme = 1, the irv downcounter is clocked by irclk, allowing car- rier modulation timing with irclk resolution. the irtxpol bit defines the starting/idle state as well as the carrier polarity for the irtx pin. if irtxpol = 1, the irtx pin is set to a logic-high when the ir timer module is enabled. if irtxpol = 0, the irtx pin is set to a logic-low when the ir timer is enabled. a separate register bit, ir data (irdata), is used to determine whether the carrier generator output is out- put to the irtx pin for the next irmt carrier cycles. when irdata = 1, the carrier waveform (or inversion of this waveform if irtxpol = 1) is output on the irtx pin during the next irmt cycles. when irdata = 0, the idle condition, as defined by irtxpol, is output on the irtx pin during the next irmt cycles. the ir timer acts as a downcounter in transmit mode. an ir transmission starts when 1) the iren bit is set to 1 when irmode = 1, 2) the irmode bit is set to 1 when iren = 1, or 3) when iren and irmode are both set to 1 in the same instruction. the irmt and irca registers, along with the irdata and irtxpol bits, are sampled at the beginning of the transmit process and every time the ir timer value reloads its value. when the irv reaches 0000h value, on the next carrier clock, it does the following: 1) reloads irv with irmt. 2) samples irca, irdata, and irtxpol. 3) generates irtx accordingly. 4) sets irif to 1. 5) generates an interrupt to the cpu if enabled (irie = 1). to terminate the current transmission, the user can switch to receive mode (irmode = 0) or clear iren to 0. carrier modulation time = irmt + 1 carrier cycles MAXQ61H 16-bit microcontroller with infrared module ______________________________________________________________________________________ 11
MAXQ61H 16-bit microcontroller with infrared module 12 ______________________________________________________________________________________ 1 0 0 1 sample irdata on irv = 0000h carrier modulation carrier generation carrier irclk ircfme ircal + 1 ircah + 1 irdata irmt irtxpol irtx pin ir interrupt figure 2. ir transmit carrier generation and carrier modulator control carrier output (irv) irdata ir interrupt 0 1 irmt = 3 0 irtx irtxpol = 1 irtx irtxpol = 0 irca irmt irmt = 5 irca = 0202h irca = 0002h irca, irmt, irdata sampled at end of irv downcount interval 31 20543210 figure 1. ir transmit frequency shifting example (ircfme = 0)
MAXQ61H 16-bit microcontroller with infrared module ______________________________________________________________________________________ 13 carrier output (irv) irdata ir interrupt irtx irtxpol = 1 irtx irtxpol = 0 0 1 0 irmt = 3 2 3102 310 figure 3. ir transmission waveform (ircfme = 0) ir transmit?ndependent external carrier and modulator outputs the normal transmit mode modulates the carrier based upon the irdata bit. however, the user has the option to input the modulator (envelope) on an external pin if desired. if the irenv[1:0] bits are configured to 01b or 10b, the modulator/envelope is output to the irtxm pin. the irdata bit is output directly to the irtxm pin (if irtxpol = 0) on each irv downcount interval bound- ary just as if it were being used to internally modulate the carrier frequency. if irtxpol = 1, the inverse of the irdata bit is output to the irtxm pin on the irv inter- val downcount boundaries. the envelope output is illus- trated in figure 4. when the envelope mode is enabled, it is possible to output either the modulated (irenv[1:0] = 01b) or unmodulated (irenv[1:0] = 10b) carrier to the irtx pin. ir receive when configured in receive mode (irmode = 0), the ir hardware supports the irrx capture function. the irrxsel[1:0] bits define which edge(s) of the irrx pin should trigger ir timer capture function. the ir module starts operating in the receive mode when irmode = 0 and iren = 1. once started, the ir timer (irv) starts up counting from 0000h when a quali- fied capture event as defined by irrxsel happens. the irv register is, by default, counting carrier cycles as defined by the irca register. however, the ir carrier frequency detect (ircfme) bit can be set to 1 to allow clocking of the irv register directly with the irclk for finer resolution. when ircfme = 0, the irca defined carrier is counted by irv. when ircfme = 1, the irclk clocks the irv register. on the next qualified event, the ir module does the following: 1) captures the irrx pin state and transfers its value to irdata. if a falling edge occurs, irdata = 0. if a rising edge occurs, irdata = 1. 2) transfers its current irv value to the irmt. 3) resets irv content to 0000h (if irxrl = 1). 4) continues counting again until the next qualified event. if the ir timer value rolls over from 0ffffh to 0000h before a qualified event happens, the ir timer overflow (irov) flag is set to 1 and an interrupt generated if enabled. the ir module continues to operate in receive mode until it is stopped by switching into transmit mode (irmode = 1) or clearing iren = 0.
MAXQ61H carrier burst-count mode a special mode reduces the cpu processing burden when performing ir learning functions. typically, when operating in an ir learning capacity, some number of carrier cycles are examined for frequency determina- tion. once the frequency has been determined, the ir receive function can be reduced to counting the number of carrier pulses in the burst and the duration of the combined mark-space time within the burst. to simplify this process, the receive burst-count mode (as enabled by the rxbcnt bit) can be used. when rxbcnt = 0, the standard ir receive capture functionality is in place. when rxbcnt = 1, the irv capture operation is dis- abled and the interrupt flag associated with the capture no longer denotes a capture. in the carrier burst-count mode, the irmt register is now used only to count quali- fied edges. the irif interrupt flag (normally used to sig- nal a capture when rxbcnt = 0) now becomes set if 16-bit microcontroller with infrared module 14 ______________________________________________________________________________________ 0 1 0000h irv carrier modulation carrier generation irclk ircfme ircal + 1 ircah + 1 interrupt to cpu irdata irrx pin reset irv to 0000h ir timer overflow ir interrupt irxrl copy irv to irmt on edge detect edge detect figure 5. ir capture irdata ir interrupt irv interval irtxm irtxpol = 1 irtxm irtxpol = 0 irmt irmt irmt irmt 01010 10 1 figure 4. external irtxm (modulator) output
ever two irca cycles elapse without getting a qualified edge. the irif interrupt flag thus denotes absence of the carrier and the beginning of a space in the receive signal. when the rxbcnt bit is changed from 0 to 1, the irmt register is set to 0001h. the ircfme bit is still used to define whether the irv register is counting sys- tem irclk clocks or irca-defined carrier cycles. the irxrl bit is still used to define whether the irv register is reloaded with 0000h on detection of a qualified edge (per the irxsel[1:0] bits). figure 6 and the descriptive sequence embedded in the figure illustrate the expect- ed usage of the receive burst-count mode. 16-bit timers/counters the MAXQ61H provides two timers/counters that sup- port the following functions: 16-bit timer/counter 16-bit up/down autoreload counter function of external pulse 16-bit timer with capture 16-bit timer with compare input/output enhancements for pulse-width modulation set/reset/toggle output state on comparator match prescaler with 2n divider (for n = 0, 2, 4, 6, 8, 10) MAXQ61H 16-bit microcontroller with infrared module ______________________________________________________________________________________ 15 1 1 4 5 6 7 8 9 to 2 3 4 6 7 5 8 9 carrier frequency calculation irrx irv irmt irmt = pulse counting irmt = pulse counting irv = carrier cycle counting capture interrupt (irif = 1). irv irmt. irv = 0 (if irxrl = 1). software sets irca = carrier frequency. software sets rxbcnt = 1 (which clears irmt = 0001 in hardware). software clears ircfme = 0 so that irv counts carrier cycles. irv is reset to 0 on qualified edge detection if irxrl = 1. software adds to irmt the number of pulses used for carrier measurement. irca x 2x counter for space can begin immediately (qualified edge resets). qualified edge detected: irmt++ irv reset to 0 if irxrl = 1. irca x 2 period elapses: irif = 1; carrier absence = space. burst mark = irmt pulses. software clears rxbcnt = 0 so that we capture on the next qualified edge. qualified edge detected: irif = 1, capture irv irmt as the burst space (plus up to one carrier cycle). software set rxbcnt = 1 as in (5). continue (5) to (8) until learning space exceeds some duration. irv rollovers can be used. figure 6. receive burst-count example
MAXQ61H general-purpose i/o the MAXQ61H provides port pins for general-purpose i/os that have the following features: cmos output drivers schmitt trigger inputs optional weak pullup to v dd when operating in input mode while the microcontroller is in a reset state, all port pins become high impedance with weak pullups disabled, unless otherwise noted. from a software perspective, each port appears as a group of peripheral registers with unique addresses. special function pins can also be used as general-pur- pose i/o pins when the special functions are disabled. for a detailed description of the special functions avail- able for each pin, refer to the part-specific user manual. the maxq family user? guide: maxq610 supplement describes all special functions available on the MAXQ61H. on-chip oscillator an external quartz crystal or a ceramic resonator can be connected between hfxin and hfxout on the MAXQ61H, as illustrated in figure 7. noise at hfxin and hfxout can adversely affect on- chip clock timing. it is good design practice to place the crystal and capacitors near the oscillator circuitry and connect hfxin and hfxout to ground with a direct short trace. the typical values of external capaci- tors vary with the type of crystal to be used and should be initially selected based on the load capacitance as suggested by the crystal manufacturer. operating modes the lowest power mode of operation for the MAXQ61H is stop mode. in this mode, cpu state and memories are preserved, but the cpu is not actively running. wake-up sources include external i/o interrupts, the power-fail warning interrupt, or a power-fail reset. any time the microcontroller is in a state where code does not need to be executed, the user software can put the MAXQ61H into stop mode. the nanopower ring oscilla- tor is an internal ultra-low-power (400na) 8khz ring oscillator that can be used to drive a wake-up timer that exits stop mode. the wake-up timer is programmable by software in steps of 125? up to approximately 8s. the power-fail monitor is always on during normal oper- ation. however, it can be selectively disabled during stop mode to minimize power consumption. this fea- ture is enabled using the power-fail monitor disable (pfd) bit in the pwcn register. the reset default state for the pfd bit is 1, which disables the power-fail moni- tor function during stop mode. if power-fail monitoring is disabled (pfd = 1) during stop mode, the circuitry responsible for generating a power-fail warning or reset is shut down and neither condition is detected. thus, 16-bit microcontroller with infrared module 16 ______________________________________________________________________________________ MAXQ61H v dd stop clock circuit r f c2 c1 hfxin hfxout rf = 1m 50% c1 = c2 = 30pf figure 7. on-chip oscillator
the v dd < v rst condition does not invoke a reset state. however, in the event that v dd falls below the por level, a por is generated. the power-fail monitor is enabled prior to stop mode exit and before code exe- cution begins. if a power-fail warning condition (v dd < v pfw ) is then detected, the power-fail interrupt flag is set on stop mode exit. if a power-fail condition is detected (v dd < v rst ), the cpu goes into reset. power-fail detection figures 8, 9, and 10 show the power-fail detection and response during normal and stop mode operation. if a reset is caused by a power-fail, the power-fail moni- tor can be set to one of the following intervals: always on?ontinuous monitoring ? 11 nanopower ring oscillator clocks (~256ms) ? 12 nanopower ring oscillator clocks (~512ms) ? 13 nanopower ring oscillator clocks (~1.024s) in the case where the power-fail circuitry is periodically turned on, the power-fail detection is turned on for two nanopower ring oscillator cycles. if v dd > v rst during detection, v dd is monitored for an additional nanopow- er ring oscillator period. if v dd remains above v rst for the third nanopower ring period, the cpu exits the reset state and resumes normal operation from utility rom at 8000h after satisfying the crystal warmup period. if a reset is generated by any other event, such as the reset pin being driven low externally or the watchdog timer, the power-fail, internal regulator, and crystal remain on during the cpu reset. in these cases, the cpu exits the reset state in less than 20 external clock cycles after the reset source is removed. MAXQ61H 16-bit microcontroller with infrared module ______________________________________________________________________________________ 17 a b c d f g h i e v dd v pfw v rst v por internal reset (active high) t < t pfw t t pfw t t pfw t t pfw figure 8. power-fail detection during normal operation
MAXQ61H 16-bit microcontroller with infrared module 18 ______________________________________________________________________________________ state power-fail internal regulator crystal oscillator sram retention comments a on off off v dd < v por. b on on on v por < v dd < v rst. crystal warmup time, t xtal_rdy . cpu held in reset. c on on on v dd > v rst . cpu normal operation. d on on on power drop too short. power-fail not detected. e on on on v rst < v dd < v pfw . pfi is set when v rst < v dd < v pfw and maintains this state for at least t pfw , at which time a power- fail interrupt is generated (if enabled). cpu continues normal operation. f on (periodically) off off yes v por < v dd < v rst. power-fail detected. cpu goes into reset. power-fail monitor turns on periodically. g on on on v dd > v rst. crystal warmup time, t xtal_rdy . cpu resumes normal operation from 8000h. h on (periodically) off off yes v por < v dd < v rst. power-fail detected. cpu goes into reset. power-fail monitor is turned on periodically. i off off off v dd < v por. device held in reset. no operation allowed. table 2. power-fail detection states during normal operation
MAXQ61H 16-bit microcontroller with infrared module ______________________________________________________________________________________ 19 state power-fail internal regulator crystal oscillator sram retention comments a on off off yes application enters stop mode. v dd > v rst. cpu in stop mode. b on off off yes power drop too short. power-fail not detected. c on on on yes v rst < v dd < v pfw. power-fail warning detected. turn on regulator and crystal. crystal warmup time, t xtal_rdy . exit stop mode. d on off off yes application enters stop mode. v dd > v rst. cpu in stop mode. e on (periodically) off off yes v por < v dd < v rst. power-fail detected. cpu goes into reset. power-fail monitor is turned on periodically. f off off off v dd < v por. device held in reset. no operation allowed. table 3. stop mode power-fail detection states with power-fail monitor enabled v pfw v rst v por a b c d e f v dd t < t pfw t t pfw t t pfw stop internal reset (active high) figure 9. stop mode power-fail detection states with power-fail monitor enabled
MAXQ61H 16-bit microcontroller with infrared module 20 ______________________________________________________________________________________ state power-fail internal regulator crystal oscillator sram retention comments a off off off yes application enters stop mode. v dd > v rst . cpu in stop mode. b off off off yes v dd < v pfw . power-fail not detected because power-fail monitor is disabled. c on on on yes v rst < v dd < v pfw . an interrupt occurs that causes the cpu to exit stop mode. power-fail monitor is turned on, detects a power- fail warning, and sets the power-fail interrupt flag. turn on regulator and crystal. crystal warmup time, t xtal_rdy . on stop mode exit, cpu vectors to the higher priority of power-fail and the interrupt that causes stop mode exit. table 4. stop mode power-fail detection states with power-fail monitor disabled v pfw v rst v por v dd a b c d e f stop internal reset (active high) interrupt figure 10. stop mode power-fail detection with power-fail monitor disabled
applications information the low-power, high-performance risc architecture of this device makes it an excellent fit for many portable or battery-powered applications. it is ideally suited for applications such as universal remote controls that require the cost-effective integration of ir transmit/ receive capability. grounds and bypassing careful pcb layout significantly minimizes system-level digital noise that could interact with the microcontroller or peripheral components. the use of multilayer boards is essential to allow the use of dedicated power planes. the area under any digital components should be a continuous ground plane if possible. keep any bypass capacitor leads short for best noise rejection and place the capacitors as close to the leads of the devices as possible. cmos design guidelines for any semiconductor require that no pin be taken above v dd or below gnd. violation of this guideline can result in a hard failure (damage to the silicon inside the device) or a soft fail- ure (unintentional modification of memory contents). voltage spikes above or below the device? absolute maximum ratings can potentially cause a devastating ic latchup. microcontrollers commonly experience negative volt- age spikes through either their power pins or general- purpose i/o pins. negative voltage spikes on power pins are especially problematic as they directly couple to the internal power buses. devices such as keypads can conduct electrostatic discharges directly into the microcontroller and seriously damage the device. system designers must protect components against these transients that can corrupt system memory. additional documentation designers must have the following documents to fully use all the features of this device. this data sheet con- tains pin descriptions, feature overviews, and electrical specifications. errata sheets contain deviations from published specifications. the user? guides offer detailed information about device features and opera- tion. the following documents can be downloaded from www.maxim-ic.com/microcontrollers . this MAXQ61H data sheet, which contains electrical/ timing specifications and pin descriptions. the MAXQ61H revision-specific errata sheet ( www.maxim-ic.com/errata ). the maxq family user's guide , which contains detailed information on core features and operation, including programming ( www.maxim-ic.com/maxqug ). the maxq family user's guide: maxq610 supplement , which contains detailed information on features specific to the MAXQ61H. MAXQ61H 16-bit microcontroller with infrared module ______________________________________________________________________________________ 21 state power-fail internal regulator crystal oscillator sram retention comments d off off off yes application enters stop mode. v dd > v rst . cpu in stop mode. e on (periodically) off off yes v por < v dd < v rst . an interrupt occurs that causes the cpu to exit stop mode. power-fail monitor is turned on, detects a power- fail, puts cpu in reset. power-fail monitor is turned on periodically. f off off off v dd < v por . device held in reset. no operation allowed. table 4. stop mode power-fail detection states with power-fail monitor disabled (continued)
MAXQ61H 16-bit microcontroller with infrared module maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. development and technical support maxim and third-party suppliers provide a variety of highly versatile, affordably priced development tools for this microcontroller, including the following: compilers integrated development environments (ides) jtag-to-serial converters for programming and debugging a partial list of development tool vendors can be found at www.maxim-ic.com/maxq_tools . technical support is available at https://support.maxim- ic.com/micro . package type package code document no. 32 tqfn-ep t3255+3 21-0140 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . thin qfn (5mm 5mm) top view 29 30 28 27 12 11 13 p0.1/int9 p0.3/int11 p0.4/int12 p0.5/tba0/tba1/int13 p0.6/tbb0/int14 14 p0.0/irtxm/int8 n.c. n.c. p1.7/int7 n.c. p1.6/int6 hfxout 12 p2.7/tdo 4567 23 24 22 20 19 18 reset v dd v dd regout p1.3/int3 p1.2/int2 p0.2/int10 n.c. 3 21 31 10 irtx p1.1/int1 32 9 irrx p1.0/int0 p2.6/tms 26 15 p1.4/int4 p2.5/tdi 25 16 p1.5/int5 p0.7/tbb1/int15 hfxin 8 17 p2.4/tck MAXQ61H *ep *exposed pad = gnd. + pin configuration

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